This invention relates to electronic up/down counters, and more particularly to means for converting the characteristics of the inputs normally processed by one type of up/down counter to the characteristics of the inputs normally processed by another type of up/down counter.
Electronic up/down counters are well-known devices, usually in the form of integrated circuits, widely used in electronic circuits processing digital information in a variety of information display and control applications.
There are two types of up/down counters commonly employed in such circuits. A first type, such as the Motorola Part No. MC14510B, receives two input signals: one input signal is a train of electric pulses representing increments of information which might represent, for example, steps taken by a stepping motor; the other input signal is a direct current logic signal indicating direction, i.e., whether the count of the pulses in the first signal is additive or subtractive. A second type of up/down counter, such as the Texas Instruments Part No. SN54192, also receives two input signals which are identical pulse trains each representing the increments of information; however, the two pulse trains are electrically displaced from one another and are typically in quadrature. The up/down counter of the second type determines direction by sensing which pulse train is leading the other.
The input information suitable for operation of the first type of up/down counter cannot be used directly to operate the second type of up/down counter; however, it would be desirable to be able to convert the inputs suitable for the first type for use with the second type. Accordingly, it is an object of the present invention to provide means for converting input information suitable for the operation of the first type of up/down counter to input information suitable for operation of the second type of up/down counter. The present invention accomplishes this object through a novel logic circuit hereinafter described.